The present invention relates in general to the manufacture of integrated circuits, and more particularly, to an electrically programmable, non-volatile memory and high-performance logic circuitry integrated in the same semiconductor chip.
The development of integration techniques, which is directed towards the production of entire electronic systems or subsystems in a single semiconductor chip, involves the ability to integrate logic circuitry with memories having a high degree of complexity. In particular, there is an increasing need to integrate non-volatile memories, particularly of the electrically-programmable and erasable type, such as flash EEPROMs, in CMOS processes for the manufacture of high-performance logic circuitry, i.e., high-speed and low-consumption circuitry.
However, a combination of this type is becoming more and more difficult to achieve from a technological point of view because of the ever more different requirements, particularly in terms of operating voltages. In fact, on the one hand, the natural development of CMOS processes for high-performance logic circuitry leads to a progressive reduction in the operating voltage to enable the dimensions of the transistors to be reduced. The reduction in dimensions and in the operating voltage leads to a corresponding reduction in the thickness of the gate oxide and in the depth of the transistor junctions. On the other hand, electrically programmable, non-volatile memories require relatively high programming voltages, and in spite of the reduction in the dimensions of the memory cells, it is not considered possible to reduce these voltage values significantly in the near future, at least as far as floating-gate non-volatile memories are concerned.
With reference, for example, to 0.25 xcexcm technology, the transistors produced by an advanced CMOS manufacturing process designed for high-performance logic circuitry are optimized for operating within a supply-voltage range from about 0.9 to 2.5 V. These transistors have gate oxides about 5 nm thick and source/drain junctions which can withstand a voltage no greater than about 8 to 10 V.
A flash EEPROM memory, on the other hand, requires a programming voltage within the range of 10 to 12 V for the programming of the memory cells. The programming voltage is even higher for other types of non-volatile memories. To be able to withstand these voltages, the transistors require gate oxides with a thickness within the range of 15 to 18 nm and source/drain junctions with breakdown voltages at least greater than the programming voltage.
It is not easy to reconcile these conflicting requirements. On the one hand, any attempt to modify the structure of the transistors within an advanced CMOS process to render them capable of withstanding the relatively high voltages required by non-volatile memories gives rise to an unacceptable reduction in the performance of the logic circuitry. On the other hand, complete duplication of the peripheral structures to produce both high-performance CMOS transistors and transistors which can withstand relatively high voltages greatly increases the number of photolithographic masks of the manufacturing process.
A method of manufacturing relatively high-density flash EEPROM memories, i.e., greater than 256 to 512 Kbits, requires two polysilicon levels. A lower level (the first poly) is used to form the floating gates of the memory cells, and an upper level (the second poly) is used to form both the control gates of the memory cells and the gates of the transistors of the memory service circuits, e.g., cell-selection, reading, and programming circuits. This method also requires at least two different gate oxide layers. One layer about 10 nm thick is formed between the surface of the substrate and the lower polysilicon level and acts as a gate oxide for the memory cells. The other layer, which is about 15 nm thick, is formed between the substrate and the upper polysilicon level and forms the gate oxide of the transistors of the service circuits.
In some methods of manufacture, to improve the performance of the memory at low supply voltages, transistors with a thin gate oxide layer (7 to 10 nm) are also provided. These transistors have gate electrodes formed from the second polysilicon level. However, in order to minimize the number of additional masks required, these transistors with thin gate oxides share many structural elements with the transistors with thicker gate oxides which control the relatively high voltages required, for example, for programming the memory cells.
When a non-volatile memory, for example, a flash EEPROM, is to be integrated by advanced CMOS manufacturing processes, the characteristics of the high-performance transistors must be preserved. In order to achieve this, the high-performance transistors cannot share structural elements with the transistors which control the relatively high voltages required by the memory cells. It is not enough to provide for the formation of two different gate oxide layers, and one or two additional masks for adjusting the threshold voltages. Additional masks would in fact be required to produce high-voltage junctions for the high-voltage transistors, and the number of additional masks could therefore easily become excessive.
In view of the prior art described above, an object of the present invention is to provide a method of integrating a non-volatile memory and high-performance logic circuitry in the same semiconductor chip.
The method provides for manufacturing of an integrated circuit comprising a memory device and a logic circuit. The method may include forming a first gate oxide layer having a first thickness on first and second portions of a semiconductor substrate which are intended, respectively, for a plurality of first transistors of the logic circuit operating at a first voltage and for a plurality of second transistors of the logic circuit operating at a second voltage less than the first voltage. A second gate oxide layer having a second thickness is formed on third portions of the semiconductor substrate for a plurality of memory cells of the memory device.
The method may further include forming a first conducting layer on the first, second and third portions of the semiconductor substrate, and selectively removing the first conducting layer from the first and third portions of the semiconductor substrate to define gate electrodes for the plurality of first transistors and floating gate electrodes for the plurality of memory cells. The first conducting layer may also removed from the second portions of the substrate.
A first dielectric layer may be formed on the first, second and third portions of the semiconductor substrate, and the first dielectric layer is selectively removed from the first and third portions of the substrate so that the first dielectric layer remains on the gate electrodes of the plurality of first transistors and on the floating gate electrodes of the plurality of memory cells. The first dielectric layer and the first gate oxide layer are also removed from the second portions of the semiconductor substrate.
A third gate oxide layer may be formed on the second portions of the semiconductor substrate having a third thickness less than the first thickness of the first gate oxide layer, and a second conducting layer may be formed on the first, second and third portions of the semiconductor substrate. The method may further include selectively removing the second conducting layer from the third portion of the semiconductor substrate to define the floating gate electrodes for the plurality of memory cells, and selectively removing the second conducting layer from the first and second portions of the semiconductor substrate to define the gate electrodes for the plurality of second transistors and to form conducting covers for the gate electrodes for the plurality of first transistors.
The first gate oxide layer may have a thickness in a range of about 100 to 300 angstroms, the second gate oxide layer may have a thickness in a range of about of about 70 to 110 angstroms, and the third gate oxide layer may have a thickness in a range of about 20 to 80 angstroms.
The memory device may comprise an EEPROM device, for example, and the logic device may comprise a CMOS logic device, for example. The plurality of first transistors may comprise at least one N-channel transistor and at least one P-channel transistor, and the plurality of second transistors may comprise at least one N-channel transistor and at least one P-channel transistor.